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low power, low noise precision fet op amp ad795 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features low power replacement for burr-brown opa111, opa121 op amps low noise 3.3 v p-p maximum, 0.1 hz to 10 hz 11 nv/hz maximum at 10 khz 0.6 fa/hz at 1 khz high dc accuracy 500 v maximum offset voltage 10 v/c maximum drift 2 pa maximum input bias current low power: 1.5 ma maximum supply current applications low noise photodiode preamps ct scanners precision l-to-v converters connection diagram nc 1 ?in 2 +in 3 ?v s 4 nc 8 +v s 7 output 6 nc 5 nc = no connect ad795 00845-001 figure 1. 8-lead soic (r) package general description the ad795 is a low noise, precision, fet input operational amplifier. it offers both the low voltage noise and low offset drift of a bipolar input op amp and the very low bias current of a fet- input device. the 10 14 common-mode impedance insures that input bias current is essentially independent of common- mode voltage and supply voltage variations. the ad795 has both excellent dc performance and a guaranteed and tested maximum input voltage noise. it features 2 pa maximum input bias current and 500 v maximum offset voltage, along with low supply current of 1.5 ma maximum. 1k 100 10 1 10 100 1k 10k frequency (hz) voltage noise spectral density (nv/ hz) 00845-002 figure 2. voltage noise spectral density furthermore, the ad795 features a guaranteed low input noise of 3.3 v p-p (0.1 hz to 10 hz) and a 11 nv/hz maximum noise level at 10 khz. the ad795 has a fully specified and tested input offset voltage drift of only 10 v/c maximum. the ad795 is useful for many high input impedance, low noise applications. the ad795 is rated over the commercial tempera- ture range of 0c to +70c. the ad795 is available in an 8-lead soic package. 50 40 30 20 10 0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 input offset voltage drift (v/c) percentage of units 00845-003 sample size = 570 figure 3. typical distribution of average input offset voltage drift
ad795 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagram ....................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? typical performance characteristics ............................................. 6 ? minimizing input current ............................................................ 11 ? circuit board notes ........................................................................ 12 ? offset nulling ............................................................................. 13 ? ac response with high value source and feedback resistance ........................................................................................................... 14 ? overload issues ............................................................................... 15 ? input protection ......................................................................... 15 ? preamplifier applications.......................................................... 16 ? minimizing noise contributions ............................................. 16 ? using a t network ..................................................................... 17 ? a ph probe buffer amplifier ................................................... 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 12/09rev. b to rev. c changes to features section and general description section . 1 changes to input bias current parameter, table 1 ...................... 3 changes to table 2 ............................................................................ 5 added thermal resistance section ............................................... 5 added table 3; renumbered sequentially .................................... 5 changes to minimizing input current section .......................... 11 changes to circuit board notes section and figure 33 ............ 12 changes to input protection section ........................................... 15 changes to ordering guide .......................................................... 18 10/02rev. a to rev. b deleted plastic mini-dip (n) package ............................ universal edits to features ................................................................................ 1 edits to specifications ...................................................................... 2 edits to absolute maximum ratings ............................................. 3 edits to ordering guide .................................................................. 3 edits to circuit board notes ........................................................... 9 edits to figure 31 .............................................................................. 9 edits to offset nulling ................................................................... 10 deleted figure 34 ............................................................................ 10 deleted low noise op amp selection tree ............................... 15 updated outline dimensions ....................................................... 15
ad795 rev. c | page 3 of 20 specifications at +25c and 15 v dc, unless otherwise noted. table 1. ad795jr parameter test conditions/comments min typ max unit input offset voltage 1 initial offset 100 500 v offset t min ? t max 300 1000 v vs. temperature 3 10 v/c vs. supply (psrr) 86 110 db vs. supply (psrr) t min ? t max 84 100 db input bias current 2 either input v cm = 0 v 1 2 pa either input at t max = 70c v cm = 0 v 23 na either input v cm = +10 v 1 na offset current v cm = 0 v 0.1 1.0 pa offset current at t max = 70c v cm = 0 v 2 na open-loop gain v o = 10 v r l 10 k 110 120 db r l 10 k 100 108 db input voltage noise 0.1 hz to 10 hz 1.0 3.3 v p-p f = 10 hz 20 50 nv/hz f = 100 hz 12 40 nv/hz f = 1 khz 11 17 nv/hz f = 10 khz 9 11 nv/hz input current noise f = 0.1 hz to 10 hz 13 fa p-p f = 1 khz 0.6 fa/hz frequency response unity gain, small signal g = ?1 1.6 mhz full power response v o = 20 v p-p, r l = 2 k 16 khz slew rate, unity gain v o = 20 v p-p, r l = 2 k 1 v/s settling time 3 to 0.1% 10 v step 10 s to 0.01% 10 v step 11 s overload recovery 4 50% overdrive 2 s total harmonic f = 1 khz distortion r1 10 k, v o = 3 v rms ?108 db input impedance differential v diff = 1 v 10 12 ||2 ||pf common mode 10 14 ||2.2 ||pf input voltage range differential 5 20 v common-mode voltage 10 11 v over maximum operating temperature 10 v common-mode rejection ratio v cm = 10 v 90 110 db t min ? t max 86 100 db output characteristics voltage r l 2 k v s ? 4 v s ? 2.5 v t min ? t max v s ? 4 v current v out = 10 v 5 10 ma short circuit 15 ma
ad795 rev. c | page 4 of 20 ad795jr parameter test conditions/comments min typ max unit power supply rated performance 15 v operating range 4 18 v quiescent current 1.3 1.5 ma 1 input offset voltage specifications are gua ranteed after 5 minutes of operation at t a = +25c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25c. for higher temperature, the current doubles every 10c. 3 gain = ?1, r1 = 10 k. 4 defined as the time required for the amplifiers output to return to normal operation after removal of a 50% overload from the amplifier input. 5 defined as the maximum continuous voltage between the inpu ts such that neither input exceeds 10 v from ground.
ad795 rev. c | page 5 of 20 absolute maximum ratings table 2. parameter rating supply voltage 18 v internal power dissipation (at t a = +25c) soic package 500 mw input voltage v s input current 1 10 ma output short-circuit duration indefinite differential input voltage +v s and ?v s storage temperature range (r) ?65c to +125c operating temperature range ad795j 0c to +70c 1 limit input current to 10 ma or less whenever the input signal exceeds the power supply rail by 0.1 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered on a 4-layer circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 8-lead soic 155 c/w esd caution
ad795 rev. c | page 6 of 20 typical performance characteristics 20 r l = 10k ? +v in ?v in 15 10 5 0 0 5 10 15 20 supply voltage (v) input common-mode range (v) 00845-004 figure 4. common-mode voltage range vs. supply voltage 20 r l = 10k ? +v out ?v out 15 10 5 0 0 5 10 15 20 supply voltage (v) output voltage range (v) 00845-005 figure 5. output voltag e range vs. supply voltage 30 25 20 15 10 5 0 10 100 1k 10k load resistance ( ? ) output voltage swing (v p-p) 00845-006 v s = 15v figure 6. output voltage swing vs. load resistance 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0 5 10 15 20 supply voltage (v) input bias current (pa) 00845-007 figure 7. input bias current vs. supply voltage 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 input bias current (pa) percentage of units 00845-008 sample size = 1058 figure 8. typical distributi on of input bias current 10 ?9 10 ?10 10 ?11 10 ?12 10 ?13 10 ?14 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) input bias current (a) 00845-009 figure 9. input bias current vs. temperature
ad795 rev. c | page 7 of 20 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 ?15 ?10 ?5 0 5 10 15 common-mode voltage (v) input bias current (pa) 00845-010 figure 10. input bias current vs. common-mode voltage 10 ?4 10 ?5 10 ?6 10 ?7 10 ?8 10 ?9 10 ?10 10 ?11 10 ?12 10 ?13 10 ?14 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 differential input voltage (v) input bias current (a) 00845-011 +i in ?i in figure 11. input bias current vs. differential input voltage 15.0 100 10 1 0.1 0.01 12.5 10.0 7.5 5.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) voltage noise (nv/ hz) current noise (fa/ hz) 00845-012 f = 1khz voltage noise current noise figure 12. voltage and current nois e spectral density vs. temperature 1k 100 10 1 1k 10 k 100k 1m 10m 100m 1g source resistance ( ? ) voltage noise (v p-p) 00845-013 noise bandwidth: 0.1hz to 10hz figure 13. input voltage noise vs. source resistance 50 40 30 20 10 0 01 23 input voltage noise (v p-p) percentage of units 00845-014 sample size = 344 f = 0.1hz to 10hz figure 14. typical distribution of input voltage noise 1k 100 10 1 1 10 100 1k 10k 100k 1m 10m frequency (hz) voltage noise (referred to input) (nv/ hz) 00845-015 figure 15. input voltage noise spectral density
ad795 rev. c | page 8 of 20 30 25 20 15 10 5 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) short-circuit current (ma) 00845-016 ?output current +output current figure 16. short-circuit cu rrent limit vs. temperature 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 34 567891011 settling time (s) output swing from 0 to v 00845-017 error 0.1% 0.01% 0.1% 0.01% figure 17. output swing and error vs. settling time 1000 900 800 700 600 500 400 300 200 100 0 ?15 ?10 ?5 0 5 10 15 input common-mode voltage (v) absolute input error voltage (v) 00845-018 figure 18. absolute input error voltage vs. input common-mode voltage 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1m 10m frequency (hz) power supply rejection (db) 00845-019 ?psrr +psrr figure 19. power supply rejection vs. frequency 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1m 10m frequency (hz) common-mode rejection (db) 00845-020 figure 20. common-mode rejection vs. frequency 120 100 80 60 40 20 0 ?20 120 100 80 60 40 20 0 ?20 10 100 1k 10k 100k 1m 10m frequency (hz) open-loop gain (db) phase margin (degrees) 00845-021 phase gain figure 21. open-loop gain and phase margin vs. frequency
ad795 rev. c | page 9 of 20 30 25 20 15 10 5 0 1k 10k 100k 1m frequency (hz) output voltage (v p-p) 00845-022 r l = 10k ? figure 22. large signal frequency response 1000 100 10 1 0.1 1k 10k 100k frequency (hz) 1m 10m closed-loop output impedance ( ? ) 00845-023 figure 23. closed-loop outp ut impedance vs. frequency ? 60 ?70 ?80 ?90 ?100 ?110 ?120 100 1k 10k 100k frequency (hz) thd (db) 00845-024 v in = 3v rms r l = 10k ? figure 24. total harmonic distortion vs. frequency 2.0 1.5 1.0 0.5 0 0 5 10 15 20 supply voltage (v) quiescent supply current (ma) 00845-025 figure 25. quiescent supply current vs. supply voltage 50 40 30 20 10 0 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 input offset voltage (v) percentage of units 00824-026 sample size = 1419 figure 26. typical distribution of input offset voltage 7 4 3 6 2 10k ? 10k ? +v s v in v out ?v s 0.1f 0.1f c l 100pf r l 10k? ad795 00845-027 figure 27. unity gain inverter
ad795 rev. c | page 10 of 20 0 0845-028 100 90 10 0% 20v 5s 5v figure 28. unity gain inverter large signal pulse response 0 0845-029 100 90 10 0% 10mv 500ns figure 29. unity gain inverter small signal pulse response 7 4 3 6 2 +v s v in v out ?v s 0.1f 0.1f c l 100pf r l 10k? ad795 00845-030 figure 30. unity gain follower 0 0845-031 100 90 10 0% 20v 5s 5v figure 31. unity gain follower large signal pulse response 0 0845-032 100 90 10 0% 20mv 500ns figure 32. unity gain follower small signal pulse response
ad795 rev. c | page 11 of 20 minimizing input current the ad795 is guaranteed to 1 pa maximum input current with 15 v supply voltage at room temperature. careful atten- tion to how the amplifier is used is necessary to maintain this performance. the amplifiers operating temperature should be kept as low as possible. like other jfet input amplifiers, the ad795s input current doubles for every 10c rise in junction temperature (illustrated in figure 9). on-chip power dissipation raises the device operating temperature, causing an increase in input current. reducing supply voltage to cut power dissipation reduces the ad795s input current (see figure 7). heavy output loads can also increase junction temperature; maintaining a minimum load resistance of 10 k is recommended.
ad795 rev. c | page 12 of 20 circuit board notes the ad795 is designed for mounting on printed circuit boards (pcbs). maintaining picoampere resolution in those environ- ments requires a lot of care. both the board and the amplifiers package have finite resistance. voltage differences between the input pins and other pins as well as pcb metal traces causes parasitic currents (see figure 33) larger than the ad795s input current unless special precautions are taken. two methods of minimizing parasitic leakages include guarding of the input lines and maintaining adequate insulation resistance. figure 34 and figure 35 show the recommended guarding schemes for noninverting and inverting topologies. pin 1 is not connected, and can be safely connected to the guard. the high impedance input trace should be guarded on both edges for its entire length. 00845-033 3 6 2 ad795 + ? v out c f v e v s i p i s r f c p r p v s i p = v s r p dc p dt dv dt c p ++ figure 33. sources of parasitic leakage currents 00845-034 notes 1. on the ?r? package pin 1, pin 5, and pin 8 are open and can be connected to analog common or to the driven guard to reduce leakage. 3 6 2 ad795 + ? v out c f i s r f guard 1 2 3 4 8 7 6 5 top view (?r? package) 8 7 6 5 figure 34. guarding schemelnverter 00845-035 guard traces input t race 1 2 3 4 8 7 6 5 ad795 top view 8 7 6 5 connect to junction of r f and r i or to pin 6 for unity gain. 2 6 3 ad795 + v out v s r f guard r i ? figure 35. guard schemefollower
ad795 rev. c | page 13 of 20 leakage through the bulk of the circuit board can still occur with the guarding schemes shown in figure 34 and figure 35. standard g10 type pcb material may not have high enough volume resistivity to hold leakages at the sub-picoampere level particularly under high humidity conditions. one option that eliminates all effects of board resistance is shown in figure 36. the ad795s sensitive input pin (either pin 2 when connected as an inverter, or pin 3 when connected as a follower) is bent up and soldered directly to a teflon? insulated standoff. both the signal input and feedback co mponent leads must also be insulated from the circuit board by teflon standoffs or low leakage shielded cable. 00845-036 ad795 1 2 3 4 8 7 6 5 ad795 8 7 6 5 input signal led pc board input pin: pin 2 for inverter or pin 3 for follower. teflon insulated standoff figure 36. input pin to insulating standoff contaminants such as solder flux on the boards surface and on the amplifiers package can greatly reduce the insulation resistance between the input pin and those traces with supply or signal voltages. both the package and the board must be kept clean and dry. an effective cleaning procedure is to first swab the surface with high grade isopropyl alcohol, then rinse it with deionized water and, finally, bake it at 100c for 1 hour. poly- propylene and polystyrene capacitors should not be subjected to the 100c bake because they can be damaged at temperatures greater than 80c. other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. keeping circuit board components rigid and minimizing vibration reduce triboelectric and piezoelectric effects. all precision high impedance circuitry requires shielding from electrical noise and interference. for example, a ground plane should be used under all high value (that is, greater than 1 m) feedback resistors. in some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. referring to the equation in figure 33, this coupling can take place in either, or both, of two different forms via time varying fields: p c d t dv or by injection of parasitic currents by changes in capacitance due to mechanical vibration: v d t dcp both proper shielding and rigid mechanical mounting of components help minimize error currents from both of these sources. offset nulling the circuit in figure 37 can be used when the amplifier is used as an inverter. this method introduces a small voltage in series with the amplifiers positive input terminal. the amplifiers input offset voltage drift with temperature is not affected. however, variation of the power supply voltages causes offset shifts. 00845-037 3 6 2 ad795 + ? v out +v s ?v s v i r i r f 499k ? 499k ? 0.1f 200? 100k ? figure 37. alternate offset null circuit for inverter
ad795 rev. c | page 14 of 20 ac response with high value source and feedback resistance source and feedback resistances greater than 100 k magnifies the effect of input capacitances (stray and inherent to the ad795) on the ac behavior of the circuit. the effects of common-mode and differential input capacitances should be taken into account because the circuits bandwidth and stability can be adversely affected. in a follower, the source resistance, r s , and input common- mode capacitance, c s (including capacitance due to board and capacitance inherent to the ad795), form a pole that limits circuit bandwidth to 1/2 r s c s . figure 38 shows the follower pulse response from a 1 m source resistance with the amplifiers input pin isolated from the board; only the effect of the ad795s input common-mode capacitance is seen. 0 0845-038 100 90 10 0% 10mv 5s figure 38. follower pulse response from 1 m source resistance in an inverting configuration, the differential input capacitance forms a pole in the circuits loop transmission. this can create peaking in the ac response and possible instability. a feedback capacitance can be used to stabilize the circuit. the inverter pulse response with r f and r s equal to 1 m and the input pin isolated from the board appears in figure 39. figure 40 shows the response of the same circuit with a 1 pf feedback capacitance. typical differential input capacitance for the ad795 is 2 pf. 0 0845-039 100 90 10 0% 10mv 5s figure 39. inverter pulse response with 1 m source and feedback resistance 0 0845-040 100 90 10 0% 10mv 5s figure 40. inverter pulse response with 1 m source and feedback resistance, 1 pf feedback capacitance
ad795 rev. c | page 15 of 20 overload issues driving the amplifier output beyond its linear region causes some sticking; recovery to normal operation is within 2 s of the input voltage returning within the linear range. if either input is driven below the negative supply, the amplifiers output is driven high, causing a phenomenon called phase reversal. normal operation is resumed within 30 s of the input voltage returning within the linear range. figure 41 shows the ad795s input bias currents vs. differential input voltage. picoamp level input current is maintained for differential voltages up to several hundred millivolts. this behavior is only important if the ad795 is in an open-loop application where substantial differential voltages are produced. 10 ?4 10 ?5 10 ?6 10 ?7 10 ?8 10 ?9 10 ?10 10 ?11 10 ?12 10 ?13 10 ?14 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 differential input voltage (v) input bias current (a) 00845-041 +i in ?i in figure 41. input bias current vs. differential input voltage input protection the ad795 safely handles any input voltage within the supply voltage range. some applications may subject the input terminals to voltages beyond the supply voltages. in these cases, the following guidelines should be used to maintain the ad795s functionality and performance. if the inputs are driven more than a 0.5 v below the minus supply, milliamp level currents can be produced through the input terminals. that current should be limited to 10 ma for transient overloads (less than 1 second) and 1 ma for continuous overloads. this can be accomplished with a protection resistor in the input terminal (as shown in figure 42 and figure 43). the protection resistors johnson noise adds to the amplifiers input voltage noise and impacts the frequency response. driving the input terminals above the positive supply causes the input current to increase and limit at 40 a. this condition is maintained until 15 v above the positive supplyany input voltage within this range does not harm the amplifier. input voltage above this range causes destructive breakdown and should be avoided. 00845-042 3 6 2 ad795 c f r p r f source figure 42. inverter wi th input current limit 00845-043 2 6 3 ad795 r p source figure 43. follower with input current limit figure 44 is a schematic of the ad795 as an inverter with an input voltage clamp. bootstrapping the clamp diodes at the inverting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. low leakage diodes (less than 1 pa), such as the fd333s should be used, and should be shielded from light to keep photocurrents from being generated. even with these precautions, the diodes measurably increase the input current and capacitance. to achieve the low input bias currents of the ad795, it is not possible to use the same on-chip protection as used in other analog devices, inc., op amps. this makes the ad795 sensitive to handling and precautions should be taken to minimize esd exposure whenever possible. 00845-044 3 6 2 ad795 r f protected diodes (low leakage) source figure 44. input voltage clamp with diodes 00845-045 3 8 6 2 ad795 10p f output 1g ? guard photodiode filtered output optional 26hz filter figure 45. ad795 used as a photodiode preamplifier
ad795 rev. c | page 16 of 20 preamplifier applications the low input current and offset voltage levels of the ad795 together with its low voltage noise make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. in a typical preamp circuit, shown in figure 45, the output of the amplifier is equal to: v out = i d (rf) = rp (p) rf where: i d is the photodiode signal current, in amps (a). rp is the photodiode sensitivity, in amps/watt (a/w). rf is the value of the feedback resistor, in ohms (). p is the light power incident to photodiode surface, in watts (w). an equivalent model for a photodiode and its dc error sources is shown in figure 46. the amplifiers input current, i b , contri- butes an output voltage error, which is proportional to the value of the feedback resistor. the offset voltage error, v os , causes a dark current error due to the photodiodes finite shunt resistance, rd. the resulting output voltage error, v e , is equal to: v e = (1 + rf/rd) v os + rf i b a shunt resistance on the order of 10 9 is typical for a small photodiode. resistance rd is a junction resistance, which typically drops by a factor of two for every 10c rise in temperature. in the ad795, both the offset voltage and drift are low, which helps minimize these errors. r d i d i b c d 50pf c f 10pf v os r f 1g ? photodiode output 00845-046 figure 46. a photodiode model showing dc error sources minimizing noise contributions the noise level limits the resolution obtainable from any preamplifier. the total output voltage noise divided by the feedback resistance of the op amp defines the minimum detectable signal current. the minimum detectable current divided by the photodiode sensitivity is the minimum detectable light power. sources of noise in a typical preamp are shown in figure 47. the total noise contribution is defined as: ? ? ?? ?? ?? ?? ?? 2 2 2 2 2 2 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ??? rfcfs rdcds rd rf en rfcfs rf isifinv out r d i s c d 50pf c f 10pf r f 1g ? photodiode output 00845-047 en i n i f i s figure 47. noise contributions of various sources figure 48, a spectral density vs. frequency plot of each sources noise contribution, shows that the bandwidth of the amplifiers input voltage noise contribution is much greater than its signal bandwidth. in addition, capacitance at the summing junction results in a peaking of noise gain in this configuration. this effect can be substantial when large photodiodes with large shunt capacitances are used. capacitor cf sets the signal bandwidth and limits the peak in the noise gain. each sources rms or root- sum-square contribution to noise is obtained by integrating the sum of the squares of all the noise sources and then by obtaining the square root of this sum. minimizing the total area under these curves optimizes the preamplifiers overall noise performance. an output filter with a passband close to that of the signal can greatly improve the preamplifiers signal to noise ratio. the photodiode preamplifier shown in figure 47, without a bandpass filter, has a total output noise of 50 v rms. using a 26 hz single-pole output filter, the total output noise drops to 23 v rms, a factor of 2 improvement with no loss in signal bandwidth. 10 v 1v 100nv 10nv 1 10 100 1k 10k 100k frequency (hz) output voltage noise (v/ hz) 00845-048 signal bandwidth with filter no filter en i n i q and i f figure 48. voltage noise spectral density of the circuit of figure 47 with and without an output filter
ad795 rev. c | page 17 of 20 using a t network a t network, shown in figure 49, can be used to boost the effective transimpedance of an i-to-v converter, for a given feedback resistor value. however, amplifier noise and offset voltage contributions are also amplified by the t network gain. a low noise, low offset voltage amplifier, such as the ad795, is needed for this type of application. 00845-049 10p f v out r f 100m ? r i 1.1k ? r g 10k? photodiode ad795 v out = i d r f (1 + ) r g r i figure 49. photodiode preamp empl oying a t network for added gain a q h probe buffer amplifier a typical ph probe requires a buffer amplifier, shown in figure 50, to isolate its 10 6 to 10 9 source resistance from external circuitry. the low input current of the ad795 allows the voltage error produced by the bias current and electrode resistance to be minimal. the use of guarding, shielding, high insulation resistance standoffs, and other such standard methods used to minimize leakage are all needed to maintain the accuracy of this circuit. the slope of the ph probe transfer function, 50 mv per ph unit at room temperature, has a 3300 ppm/c temperature coefficient. the buffer of figure 50 provides an output voltage equal to 1 v/ph unit. temperature compensation is provided by resistor rt, which is a special temperature compensation resistor, part number q81, 1 k, 1%, 3500 ppm/c, available from tel labs, inc. 00845-050 2 8 7 1 4 5 6 3 ad795 output 1v/ph unit 19.6k ? rt 1k? 3500ppm/c v os adjust 100k ? guard ?v s +v s 0.1f 0.1f +v s ?v s +15v com ?15v ph probe figure 50. ph probe amplifier
ad795 rev. c | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 51. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ad795jr 0c to +70c 8-lead soic_n r-8 AD795JR-REEL 0c to +70c 8-lead soic_n r-8 AD795JR-REEL7 0c to +70c 8-lead soic_n r-8 ad795jrz 0c to +70c 8-lead soic_n r-8 ad795jrz-reel 0c to +70c 8-lead soic_n r-8 ad795jrz-reel7 0c to +70c 8-lead soic_n r-8 1 z= rohs compliant part.
ad795 rev. c | page 19 of 20 notes
ad795 rev. c | page 20 of 20 notes ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00845-0-12/09(c)

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